In pursuit of improving semiconductor digital logic devices, there is a continual quest to define and produce transistors having ever smaller overall cell geometries and that are capable of operating at ever increasing switching speeds. Cell geometry is here defined as the two-dimensional surface area required for the implementation of a single, integral, active logic element, typically a single N- or P-channel transistor or a pair of complementary transistors. Cell geometry is distinguished from transistor geometry in that the latter refers to the three-dimensional structure of a single, integral active logic element.
Reduced cell geometry is naturally desired to increase cell packing density that, in turn, permits ever increased levels of device integration and corresponding logic system complexity and capability. Increases in operating speed are naturally advantageous regardless of the level of integration realized. Conveniently, these desires are complementary in that a major factor in the operating speed of a field effect transistor is the channel length defined by its transistor geometry. Reduction of channel length results in a corresponding reduction in the time required for charge carriers to transit between the transistor source and drain regions and, to at least a first approximation, the switching speed of the transistor.
There are, however, numerous other complications involved in obtaining high switching speed, small cell geometry transistors. These complications include excessive power dissipation and the onset of short channel effects. Power dissipation is naturally a problem as the sheer number of transistors packed together on a common monolithic substrate increases. Practical construction constraints limit the rate at which power dissipated as heat can be removed from the vicinity of the transistors. A typical manner of dealing with this problem involves reducing the operating potential difference applied to the transistors so as to effect a corresponding decrease in the power dissipated. There is, however, a practical limit to the reduction of the operating potential difference before there is a corresponding degradation of the transistor's operating characteristics, particularly including its switching speed. Again conveniently, this practical limit also tends to decrease as the cell dimensions are reduced.
Short channel effects encountered typically include decreased operating device breakdown voltages, hot carrier effects, punch-through shorting of the transistor and other effects of lesser significance. These short channel effects are generally related to the channel length of the transistor and the electric field strength induced between the source, drain and gate as a result of the applied operating potential difference. Where the electric field is of sufficient strength at the drain/substrate interface, avalanche breakdown will occur leading to the sudden destruction of the transistor. Similarly, if the depletion regions generally associated with the source and drain regions, as induced by the application of the operating potential difference, extend sufficiently toward one another to overlap, then a current punch-through condition will occur wherein the source and drain are effectively shorted together. Again, generally there will be sudden catastrophic destruction of the transistor.
A much less sudden, though equally deleterious short channel effect occurs as the result of the generation of hot carriers near the gate oxide/semiconductor substrate interface. Hot carriers are charge carriers that have been energized by the applied electric field sufficiently to overcome the potential barrier at the oxide/substrate interface. Consequently, the charge carriers are injected directly into the gate oxide where they thereafter remain trapped. As such, the gate operating characteristics of the transistor are progressively degraded from their intended nominal values over the operating lifetime of the transistor.
The short channel effects are also typically handled by reducing the applied operating potential difference so as to reduce the strength of the electrical field established in the transistor. Additionally, the punch-through effect is specifically addressed by generally increasing the doping density within the channel region. This results in an increase in the operating potential difference required to establish overlapping source and drain depletion regions.
The hot carrier effect may be further specifically addressed by providing a very shallow, lightly doped drain (LDD) region at the gate oxide/substrate interface closest to the point within the transistor where the greatest electric field strength occurs. Devices constructed with LDD regions are shown in U.S. Pat. Nos. 4,282,648 and 4,366,613. The provision of such a lightly doped region effectively reduces the electrical field strength adjacent the oxide/substrate interface. Typically, the lightly doped drain region is extremely shallow so as to minimally impact all other electrical characteristics of the drain to channel interface and very lightly doped so as to maximize the corresponding reduction of the electrical field strength within the lightly doped drain region. This reduction in field strength directly reduces the transfer of energy to charge carriers at the oxide/substrate interface with a corresponding reduction in the number of charge carriers injected into the gate oxide. The generation of any hot carriers deeper in the substrate is generally of no concern as they remain in the channel while moving between the source and drain regions. Indeed, it is typically preferred that some hot carriers be generated within the substrate as a tolerable consequence to utilizing an electrical field strength sufficient to move charge carriers between the source and drain regions at an optimally maximum velocity.
In certain applications, reduction of the operating potential difference is not an acceptable solution to dealing with the problems generally described above. Rather, provision must be made for at least some of the transistors present on the common substrate to operate from substantially increased potential differences. Exemplary of these applications are programmable memory devices such as electrically programmable read only memories (EPROM) and floating gate electrically erasable programmable read only memories (EEPROM). In these applications there is a positive desire to greatly increase the packing density of the transistors utilized as memory cells. At the same time, however, there is a positive requirement that a high voltage be tolerated by the transistors as is required whenever their corresponding memory cells are programmed and, where applicable, electrically erased. Typically, current EPROM devices require a programming voltage of between 10 and 20 volts to effect programming. EEPROM devices require programming and erasure voltages typically of between 15 to 25 volts.
Since small cell geometry, high speed transistors are preferably operated at voltages substantially less than 5 volts, typically on the order of 2-4 volts, they cannot be used. Instead, transistors having significantly different deep junction transistor and large cell geometries are typically utilized so that, with their longer channel lengths, the high programming and erasure voltages can be better tolerated. This, however, typically precludes or substantially complicates the use of high speed optimized transistor geometry transistors on the same monolithic memory chip. Thus, the high voltage tolerance is gained at the substantial expense of the total device memory capacity and a substantial reduction in circuit performance. This result is not as desirable as if substantially smaller cell geometry, high speed transistors could be used monolithically with large cell geometry transistors where specifically required for high voltage tolerance.